The fast packet switching techniques, called ATM from the first letters of the wording in the English language "Asynchronous Transfer Mode", is going to take on an ever growing importance in the integrated switching of digital streams, belonging to the services for speech signal transmission, video and data signals, with different bandwith requirements and differentiated traffic characteristics. The network foreseeing this kind of service integration, with even more wide bandwith, is called B-ISDN (Broadband Integrated Service Digital Network). This technique meets better than others the requirements of the above mentioned services using an integrated switching structure, open to possible future services with not yet defined characteristics. The resources offered by the switching system are not strictly dedicated to a single call for its all length of time, as in the circuit switching systems, but are used only on demand, when the need arises to transfer information.
As known, this technique foresees that information relevant to the various services is organised in contiguous units with a fixed length of approximately 400 bits, called cells. These are composed by information field and a routing field, called header, carrying the information necessary to the route selection through the connection network and other service information.
Cells are received by line interfaces placed at the input of a switching node, essentially consisting of a control unit and of a structure performing the real switching function. The control unit performs all high level functions related to the call processing, to the configuration of the connection network and to the control of other services. Among these functions, a fundamental is the path finding. This path is decided at the call setup phase and is common to all the cells belonging to the same call. The choice is determined call by call by routing bounds throughout the geographical network and by the bandwith allocation state within the interconnection network.
The structure performing the cells switching operates by converting the header, which validity is just link by link, and the routing of cells of the same call towards the appropriate output through the connection network.
The connection network, which has the function to obtain the space switching of the cells from an input port to an output port, must be able to deliver large traffic volumes, in the range of some hundred Gbit/s, with a low cell loss probability, and low blocking probability. Furthermore, the connection network must show a minimum crossing time and has to be open to further modular growth.
Some connection networks are known at present, based on multistage structures almost non blocking, which employ unblocking switching elements of NN capacity, where N is higher equal to 8.
Each one of these elements controls the space switching of the cells belonging to the same call, which are sent following a path unique per each input-output pair. It works in a self-routing way, since a portion of the header of the cell, called TAG, describes the route of the cell itself through the connection network and in particular the output port of each element, where the cell has to be delivered.
Since it can occur that two or more cells, arrived at different inputs, want to access to the same output port at the same time, it is necessary to foresee an intermediate storage function for the cells which cannot be immediately transferred. One cell can therefore be sent at once to the subsequent stage, while the remaining ones stand-by waiting for the availability of the output port. The known switching elements essentially differ in the way the intermediate storage of cells in conflict is performed.
According to a first method, cells are held in intermediate storages before being sent to the output through a space switching network. The storage memory is usually organized according to a FIFO discipline, in order to prevent inversions in the cells order; however this method has a drawback; in fact if the first cell which entered the memory cannot be switched due to an output conflict, it blocks all the cells arrived later, even if these are adressed towards available outputs. This can be overcome, as described in "Considerations on the structure of an ATM switch in the frame work of a hybrid BB ISDN concept", by Karl Anton Lutz, presented at IEEE COMSOC International Workshop, Nov. 22-24, 1987, Osaka, Japan, using an access algorithm to the memories, not merely FIFO, but this requires a higher complexity of memory control units.
According to another method, described in the paper titled "The Knockout switch: a simple, modular architecture for high-performance packet switching", by Y. S. Yeh and others, published in section B10.2.1 of the proceedings of 1987 ISS, Mar. 15-20, 1987, Phoenix, Ariz., USA, cells are switched towards the desired output through a crosspoint-type network performed through some buses, which operates at a speed higher than the network speed and sufficient to enable, in the worst case, to receive a cell from each input by an output. In particular, the speed increases in proportion to the number of inputs and outputs; that can originate increasing difficulties in the realization of the connection network.
A third method, described in the paper titled "Prelude: an asynchronous time-division switched network", by J. Coudreuse and others, published at section 22.2.1 of the proceeding of the 1987 ICC conference of Jun. 8, 1987, Seattle, USA, foresees that all incoming cells are entered in a common memory in the switching element and that cells are drawn from the same, through an adequate control algorithm, already switched to be sent to the appropriate output. The storage is thus considered as an area to which each output port can have free access; this storage is therefore completely shared by all output ports. On the contrary, each input port is able to enter only to a dedicated area, so whenever this area fills up, the subsequent cells arriving to that input cannot fill up other free storage areas, assigned to other inputs. Therefore the capacity of the common storage cannot be completely employed.
Moreover, due to the way cells are stored, the capacity of each memory element must be equal to the number of 8-bit bytes of the cell, which heavily decreases the system flexibility in view of possible format modifications of the cells to be treated.
Finally it must be highlighted that, with equal performances from the loss probability point of view and on equal traffic conditions, the storage schemes realized in the first two solutions require a storage capacity globally higher than the one necessary in the third solution, since storage is not shared in any way, neither at input nor at output. The structures proposed in the article "A shared buffer memory switch for an ATM exchange", by Hiroshi Kuwahara and others, published at sect. 4.4.1 of the proceedings of ICC89 conference, Jun. 11-14, 1989, Boston, USA and in "Switching ATM in a Broadband ISDN", by A. J. Wiley, published on page 115 of the proceedings of Network 89 conference, Birmingham, Great Britain, can also be considered, in which cells storage is such to enable the access to a same storage area by all input and output streams, with a consequent save in the required total storage capacity. The realization of the shared access in the storage area is also such to entirely free the number of the inputs and outputs of the elements from the cell length. Access is controlled by a control unit employing a second storage area, where pointer linked lists to the data memory are realized. However, these solutions require in the second storage area an operational speed at least double than that required in the data memory.